Parallel-to-serial data transmission is known in which parallel data including a plurality of bits (for example, 16 bits) is converted into single-bit serial data synchronized with a certain clock (CLK) signal and output.
In recent years, in data transfer between computer devices or the like, a technique has been proposed in which parallel-to-serial conversion circuits are provided for a plurality of channels (lanes). In this technique, data transmission is executed while high-speed serial data transmission lanes, which are the outputs of the channels, are arranged parallel to one another as a group. By executing the data transmission using the high-speed serial data transmission lanes arranged parallel to one another as a group, the transmission capacity and the transmission speed relating to the data transfer are improved, thereby improving the transmission efficiency in the data transmission.
When the data transmission is executed using the plurality of high-speed serial data transmission lanes arranged parallel to one another as a group, skew in output data that occurs between the lanes poses a problem. In order to describe this problem, diagrams illustrating data skew that occurs between the lanes are provided in FIGS. 7 and 8.
FIG. 7 is a schematic block diagram illustrating a transmission path provided with parallel-to-serial conversion circuits (P/S conversion circuits 100) in a plurality of lanes (in FIG. 7, three lanes). For example, pieces of 8-bit parallel data (PD0 to PD2) are input to the P/S conversion circuits 100 in the lanes, respectively. Pieces of serial data after P/S conversion, which are the outputs of the lanes, are single-bit data strings obtained by adjusting the pieces of input 8-bit parallel data using a CLK signal. The pieces of serial data (SD0 to SD2), which are the outputs of the lanes, change at unit intervals defined by the CLK cycle and are output in synchronization with the CLK cycle. As illustrated in FIG. 7, when the transmission path includes a plurality of lanes, the pieces of data (SD0 to SD2) to be output may be synchronized with one another by inputting the same CLK signals to the plurality of lanes.
However, even if the synchronization between the lanes is realized by using the same CLK signals, differences in timing or the like are caused between the outputs of the lanes because of differences in wiring capacity and differences in processing of delay between the plurality of P/S conversion circuits. As a result, skew, which is differences in timing, undesirably occurs between serial data strings, which are intended to be output in synchronized with one another. In data transmission using the plurality of lanes between which skew has occurred, an error may be caused. FIG. 8 is a timing chart illustrating a state in which skew has occurred between the plurality of lanes of output data.
The P/S conversion circuits 100 in Lanes 0 to 2 receive the pieces of 8-bit parallel data (PD0 to PD2), respectively, synchronized with one another. The piece of parallel data PD0 is input to Lane 0. The piece of parallel data PD1 is input to Lane 1. The piece of parallel data PD2 is input to Lane 2. The piece of parallel data PD0 has data strings A0, B0, and C0, each having a bit value that changes between 0 and 1 in a certain cycle. The piece of parallel data PD1 has data strings A1, B1, and C1 whose bit values change in the same timing as those of the piece of parallel data PD0. The piece of parallel data PD2 has data strings A2, B2, and C2 whose bit values change in the same timing as those of the pieces of parallel data PD0 and PD1.
The piece of parallel data PD0 has the data strings in which 8-bit data blocks [A00 to A07], [B00 to B07], and [C00 to C07] are sequentially arranged. The piece of parallel data PD1 has the data strings in which 8-bit data blocks [A10 to A17], [B10 to B17], and [C10 to C17] are sequentially arranged. The piece of parallel data PD2 has the data strings in which 8-bit data blocks [A20 to A27], [B20 to B27], and [C20 to C27] are sequentially arranged. In the configuration of the data blocks, for example, “A07” indicates a high-order bit and “A00” indicates a low-order bit.
Since the same CLK signals are supplied to the lanes, the pieces of serial data (SD0 to SD2), which are output in synchronization with the CLK signals, are synchronized with one another between the lanes. For example, when the bit value of the piece of serial data SD0 in Lane 0 is [A00], bit values of [A10] and [A20] are output from Lanes 1 and 2, respectively. This holds true for the data strings B0, B1, and B2, and the data strings C0, C1, and C2. That is, the bit values [B00, B10, and B20] and the bit values [C00, C10, and C20] are sequentially output in this order.
However, if skew occurs between the lanes, the output values that have been synchronized with one another between the serial data strings (SD0 to SD2), which are the outputs of the lanes, respectively, deviate from one another. For example, the bit values that would otherwise be arranged as [A07, A17, and A27] between the lanes and output may be output while deviating from one another as illustrated in FIG. 8. As illustrated in FIG. 8, the bit values of the lanes between which the skew has occurred may become, for example, [A07, A10, and A26], deviating from one another between the lanes. As a result, when data transmission is executed while arranging the serial data outputs of the plurality of lanes parallel to one another as a group as illustrated in FIG. 7, an incorrect piece of data may be transmitted.
The following is reference documents:    [Document 1] Japanese Laid-open Patent Publication No. 9-55667    [Document 2] Japanese Laid-open Patent Publication No. 2002-152053.